1 the SY100EP14U is a high-speed, 2ghz differential pecl/ecl 1:5 fanout buffer optimized for ultra-low skew applications. within device skew is guaranteed to be less than 25ps over temperature and supply voltage. the wide supply voltage operation allows this fanout buffer to operate in 2.5v, 3.3v, and 5v systems. a v bb reference is included for single-supply or ac-coupled pecl/ecl input applications, thus eliminating resistor networks. when interfacing to a single-ended or ac-coupled pecl/ecl input signal, connect the v bb pin to the unused /clk pin, and bypass the pin to v cc through a 0.01 f capacitor. the SY100EP14U features a 2:1 input mux, making it an ideal solution for redundant clock switchover applications. if only one input pair is used, the other pair may be left floating. in addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. enable or disable state is initiated only after the outputs are in a low state, thus eliminating the possibility of a ?unt clock pulse. the SY100EP14U i/o are fully differential and 100k ecl compatible. differential 10k ecl logic can interface directly into the SY100EP14U inputs. the SY100EP14U is part of micrel? high-speed clock synchronization family. for applications that require a different i/o combination, consult the micrel website at www.micrel.com, and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators. features description rev.: a amendment: /0 issue date: september 2001 pin configuration/block diagram clockworks SY100EP14U final 1 q0 /q0 q1 /q1 q2 /q2 q3 /q3 q4 /q4 20 vcc /en vcc /clk1 clk1 vbb /clk0 clk0 sel vee 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 10 d q tssop top view guaranteed ac parameters over temp/voltage: > 2ghz f max < 25ps within-device skew < 275ps tr/tf time < 525ps prop delay 2:1 differential mux input flexible supply voltage: 2.5v/3.3v/5v wide operating temperature range: ?0 c to +85 c v bb reference for single-ended or ac-coupled pecl inputs 100k ecl compatible outputs inputs accept pecl/lvpecl/ecl/hstl logic 75k ? internal input pull-down resistors available in a 20-pin tssop package 2.5v/3.3v/5v 1:5 lvpecl/pecl/ecl/hstl 2ghz clock driver with 2:1 differential input mux
2 clockworks SY100EP14U micrel pin description pin function clk0, /clk0 pecl, lvpecl, ecl, lvecl, hstl clock or data inputs. clk1, /clk1 internal 75k ? pull-down resistors on clk0, clk1, and internal 75k ? pull-up and 75k ? pull-down resistors or /clk0, /clk1. for single-ended applications, connect signal into clk0 and/or clk1 inputs. /clk0, /clk1 default condition is v cc /2 when left floating. clk0, clk1 default condition is low when left floating. q0 to q4 lvpecl, pecl, ecl differential outputs: terminate with 50 ? to v cc 2v. for single-ended applications, /q0 to /q4 terminate the unused output with 50 ? to v cc 2v /en lvpecl, pecl, ecl compatible synchronous enable: when /en goes high, the q out will go low and /q out will go high on the next low input clock transition. includes a 75k ? pull-down. default state is low when left floating. the internal latch is clocked on the falling edge of the input clock (clk0, clk1) sel lvpecl, pecl, ecl compatible 2:1 mux input signal select: when sel is low, clk0 input pair is selected. when sel is high, clk1 input pair is selected. includes a 75k ? pull-down. default state is low and clk0 is selected. v bb output reference voltage: equal to v cc 1.7v (approx.), and used for single-ended input signals or ac-coupled applications. for single-ended pecl, lvpecl applications, bypass with a 0.01 f to v cc . for single-ended lvttl inputs, bypass to gnd. max. sink/source current is 0.5ma. v cc positive power supply: bypass with 0.1 f//0.01 f low esr capacitors. v ee negative power supply: lvpecl, pecl applications, connect to gnd. clk_sel active input 0 clk0, /clk0 1 clk1, /clk1 function table truth table (1) clk0 clk1 clk_sel /en q lx lll hx l lh xl hll xh hlh xx xhl* note: 1. on next negative transition of clk0 or clk1.
3 clockworks SY100EP14U micrel symbol rating value unit v cc v ee power supply voltage 6.0 v v in input voltage (v cc = 0v, v in not more negative than v ee ) 6.0 to 0 v input voltage (v ee = 0v, v in not more positive than v cc ) +6.0 to 0 i out output current continuous 50 ma surge 100 i bb v bb sink/source current (2) 0.5 ma t a operating temperature range 40 to +85 c t store storage temperature range 65 to +150 c ja package thermal resistance still-air (single-layer pcb) 115 (junction-to-ambient) still-air (multi-layer pcb) 75 c/w 500lfpm (multi-layer pcb) 65 jc package thermal resistance 21 c/w (junction-to-case) absolute maximum ratings (1) notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional opera tion is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng con ditions for extended periods may affect device reliability. 2. due to the limited drive capability, use for inputs of same package only. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v cc power supply voltage v (pecl) 4.5 5.0 5.5 4.5 5.0 5.5 4.5 5.0 5.5 (lvpecl) 2.37 3.3 3.8 2.37 3.3 3.8 2.37 3.3 3.8 (ecl) 4.5 5.0 5.5 4.5 5.0 5.5 4.5 5.0 5.5 (lvecl) 3.8 3.3 2.37 3.8 3.3 2.37 3.8 3.3 2.37 i cc power supply current 75 68 78 82 ma i ih input high current 150 150 150 av in = v ih i il input low current d 0.5 0.5 0.5 av in = v il /d 150 150 150 av in = v il c in input capacitance (tssop) 0.75 pf dc electrical characteristics (1) notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.
4 clockworks SY100EP14U micrel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage (2) 555 875 555 875 555 875 mv (single-ended) v ih input high voltage (2) 1335 1620 1335 1620 1335 1620 mv (single-ended) v ol output low voltage 555 680 805 555 680 805 555 680 805 mv 50 ? to v cc 2v v oh output high voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc 2v v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (3) (100kep) lvpecl dc electrical characteristics (1) v cc = 2.5v 5%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output var ies 1:1 with v cc . 2. v bb reference is not functional for v cc < 3.0v. external v bb equivalent is required. 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1355 1675 1355 1675 1355 1675 mv (single-ended) v ih input high voltage 2075 2420 2075 2420 2075 2420 mv (single-ended) v ol output low voltage 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv 50 ? to v cc 2v v oh output high voltage 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv 50 ? to v cc 2v v bb reference voltage (2) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v cc = 3.3v v ihcmr input high voltage 1.2 v cc 1.2 v cc 1.2 v cc v common mode range (3) (100kep) lvpecl dc electrical characteristics (1) v cc = 3.3v 10%; v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output var ies 1:1 with v cc . 2. single-ended input operation is limited v cc 3.0v in lvpecl mode. v bb reference varies 1:1 with v cc . 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
5 clockworks SY100EP14U micrel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 3055 3375 3055 3375 3055 3375 mv (single-ended) v ih input high voltage 3775 4120 3775 4120 3775 4120 mv (single-ended) v ol output low voltage 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv 50 ? to v cc 2v v oh output high voltage 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv 50 ? to v cc 2v v bb output voltage reference (2) 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v cc = +5.0v v ihcmr input high voltage (3) 2.0 v cc 2.0 v cc 2.0 v cc v common mode range (100kep) pecl dc electrical characteristics (1) v cc = 5.0v 10%, v ee = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output par ameters are at v cc = 5.0v. they vary 1:1 with v cc . 2. v bb reference varies 1:1 with vcc. 3. the v ihcmr range is referenced to the most positive side of the differential input signal. single-ended input clk pin operation is limite d to v cc 3.0v in pecl mode. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1945 1625 1945 1625 1945 1625 mv (single-ended) v ih input high voltage 1165 880 1165 880 1165 880 mv (single-ended) v ol output low voltage 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv 50 ? to v cc 2v v oh output high voltage 1145 1020 0895 1145 1020 0895 1145 1020 0895 mv 50 ? to v cc 2v v bb output reference voltage (2) 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage v common mode range (3) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 (100kep) lvecl dc electrical characteristics (1) v ee = 2.37v to 3.8v; v cc = 0v notes: 1. 100kep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establ ished. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output par ameters vary 1:1 with v cc . 2. single-ended input operation is limited v ee 3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . 3. v ihcmr (min) varies 1:1 with v ee , v ihcmr (max) varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal.
6 clockworks SY100EP14U micrel (100k) ecl/lvecl dc electrical characteristics (1) v cc = 0v, v ee = 5.5v to 3.0v notes: 1. 10ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. the circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained. input and output paramete rs vary 1:1 with v cc . 2. all loading with 50 ? to v cc 2.0v. 3. single-ended input operation is limited v ee 3.0v in ecl/lvecl mode. v bb reference varies 1:1 with v cc . 4. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . the v ihcmr is referenced to the most positive side of the differential input signal. t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition v il input low voltage 1945 1625 1945 1625 1945 1625 mv v ih input high voltage 1225 880 1225 880 1225 880 mv v ol output low voltage (2) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv 50 ? to v cc 2v v oh output high voltage (2) 1145 1020 895 1145 1020 895 1145 1020 895 mv 50 ? to v cc 2v v bb output reference voltage (3) 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage v common mode range (4) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv v x input crossover voltage 680 900 680 900 680 900 mv hstl input dc electrical characteristics v cc = 2.37v to 3.8v; v ee = 0v
7 clockworks SY100EP14U micrel t a = ?0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit f max maximum frequency (1) 2 2 2 ghz t plh pecl/ecl (v cc = 5v) t phl propagationdelay to output in (differential) 250 330 400 250 330 450 250 330 600 ps in (single-ended) 355 ps lvpecl/lvecl ( v cc = 2.37v to 3.8v) propagation delay to output in (differential) 275 350 425 275 350 475 275 350 525 ps in (single-ended) 375 ps t skew (2) pecl/ecl (v cc = 5v) within-device skew (diff.) 25 35 30 45 40 50 ps part-to-part skew (diff.) 100 125 150 175 175 200 ps lvpecl/lvecl ( v cc = 2.37v to 3.8v) within-device skew (diff.) 10 25 15 25 15 25 ps part-to-part skew (diff.) 100 125 150 175 200 225 ps t s set-up time (3) /en to clk 100 50 100 50 100 50 ps t h hold time (3) /en to clk 200 140 200 140 200 140 ps t jitter cycle-to-cycle jitter (rms) 0.2 <1 0.2 <1 0.2 <1 ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r , t f pecl/ecl output rise/fall times (20% to 80%) 100 180 240 105 180 270 110 225 300 ps lvpecl/lvecl ( v cc = 2.37v to 3.8v) 90 130 225 95 130 250 100 150 275 ps ac electrical characteristics lvpecl: v cc = 2.37v to 2.625v, v ee = 0v; pecl: v cc = 4.50v to 5.50v, v ee = 0v; ecl: v ee = 4.50v to 5.5v, v cc = 0v; lvecl:v ee = 2.37v to 3.8v, v cc = 0v notes: 1. f max is defined as the maximum toggle frequency. measured with 750mv input signal, 50% duty cycle, all loading with 50 ? to v cc 2v. 2. skew is measured between outputs under identical transitions. 3. set-up and hold times apply to synchronous applications that intend to enable/disable before then ext clock cycle. for asynch ronous applications, set- up and hold time does not apply. product ordering code ordering package operating package code type range marking SY100EP14Uk4i k4-20-1 industrial xep14u SY100EP14Uk4itr* k4-20-1 industrial xep14u *tape and reel
8 clockworks SY100EP14U micrel termination recommendations r2 82 ? r2 82 ? z o = 50 ? z o = 50 ? +3.3v +3.3v v t = v cc 2v r1 130 ? r1 130 ? +3.3v figure 1. parallel termination?hevenin equivalent notes: 1. for +2.5v systems: r1 = 250 ? r2 = 62.5 ? 2. for +5.0v systems: r1 = 82 ? r2 = 130 ? z = 50 ? z = 50 ? 50 ? 50 ? 50 ? +3.3v +3.3v source destination r b figure 2. three-resistor ??ermination notes: 1. power-saving alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . for +3.3v systems r b = 46 ? to 50 ? . for +5v systems, r b = 110 ? . +3.3v +3.3v 50 ? z o = 50 ? 0.01 f v bb r2 82 ? +3.3v +3.3v r1 130 ? r1 130 ? r2 82 ? v t = v cc 2v q /q +3.3v figure 3. terminating unused i/o notes: 1. unused output (/q) must be terminated to balance the output. 2. micrel's differential i/o logic devices include a v bb reference pin . 3. connect unused input through 50 ? to v bb . bypass with a 0.01 f capacitor to v cc , not gnd. 4. for +2.5v systems: r1 = 250 ? , r2 = 62.5 ? .
9 clockworks SY100EP14U micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2001 micrel incorporated 20 lead tssop (k4-20-1) .10 .004 + .10 .00 + .004 .000 .05 0.002 + .10 .00 + .004 .000 .10 .004 rev. 01
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